View AS5SS256K18DQ-10IT_1776038.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 ssram as5ss256k18 austin semiconductor, inc. features ? fast access times: 8, 10, and 15ns ? fast clock speed: 113, 100, and 66 mhz ? fast clock and oe\ access times ? single +3.3v +0.3v/-0.165v power supply (v dd ) ? snooze mode for reduced-power standby ? common data inputs and data outputs ? individual byte wrtie control and global write ? three chip enables for simple depth expansion and address pipelining ? clock-controlled and registered addresses, data i/os and control signals ? interally self-timed write cycle ? burst control pin (interleaved or linear burst) ? automatic power-down ? low capacitive bus loading ? operating temperature ranges: - military -55 o c to +125 o c - industrial -40 o c to +85 o c options marking ? timing 7.5ns/8ns/113 mhz -8* 8.5ns/10ns/100 mhz -9 10ns/15ns/66 mhz -10 ? packages 100-pin tqfp dq no. 1001 ? operating temperature ranges: - military -55 o c to +125 o cit - industrial -45 o c to +85 o cxt *available as it only. 256k x 18 ssram synchronous burst sram, flow-through pin assignment (top view) 100-pin tqfp for more products and information please visit our web site at www.austinsemiconductor.com sa sa ce\ ce2 nc nc bwb\ bwa\ ce2\ v dd v ss clk gw\ bwe\ oe\ adsc\ adsp\ adv\ sa sa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 nc nc nc v dd q v ss nc nc dqb dqb v ss v dd q dqb dqb v ss v dd nc v ss dqb dqb v dd q v ss dqb dqb dqpb nc v ss v dd q nc nc nc sa nc nc v dd q v ss nc dqpa dqa dqa v ss v dd q dqa dqa v ss nc v dd zz dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc mode sa sa sa sa sa1 sa0 dnu dnu v ss v dd nf** nf** sa sa sa sa sa sa sa general description the austin semiconductor, inc. synchronous burst sram family employs high-speed, low power cmos designs that are fabricated us- ing an advanced cmos process. asis 4mb synchronous burst srams integrate a 256k x 18, sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (clk). the synchronous inputs include all addresses, all data inputs, active low chip enable (ce\), two additional chip enables for easy depth expansion (ce2\, ce2), burst control inputs (adsc\, adsp\, adv\), byte write enables (bwx\) and global write (gw\). asynchronous inputs include the output enable (oe\), clock (clk) and snooze enable (zz). there is also a burst mode input (mode) that selects between interleaved and linear burst modes. the data-out (q), enabled by oe\, is also asynchronous. write cycles can be from one to two bytes wide, as controlled by the write control inputs. burst operation can be initiated with either address status processor (adsp\) or address status controller (adsc\) inputs. subsequent burst addresses can be internally generated as controlled by the burst ad- vance input (adv\). address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during write cycles on this x18 device bwa\ controls dqa pins and dqpa; bwb\ controls dqb pins and dqpb. gw\ low causes all bytes to be written. parity bits are available on this device. asis 4mb synchronous burst srams operate from a +3.3v v dd power supply, and all inputs and outputs are ttl-compatible. the de- vice is ideally suited for 486, pentium?, and powerpc systems and those systems that benefit from a wide synchronous data bus. **pins 42,43 reserved for future address expansion for 8mb, 16mb densities.
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 ssram as5ss256k18 austin semiconductor, inc. pin descriptions pin numbers sym type description 37, 36, 32-35, 44-50, 80-82, 99, 100 sa0, sa1, sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of clk. 93, 94 bwa\ bwb\ input synchronous byte write enables: these active low inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of clk. a byte write enables is low for a write cycle and high for a read cycle. bwa\ controls dqa pins and dqpa; bwb\ controls dqb pins and dqpb. 87 bwe\ input byte write enable: this active low input permits byte write operations and must meet the setup and hold times around the rising edge of clk. 88 gw\ input global write: this active low input allows a full 18-bit write to occur independent of the bwe\ and bwx\ lines and must meet the setup and hold times around the rising edge of clk. 89 clk input clock: this signal registers the addresses, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clocks risin g ed g e. 98 ce\ input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp\. ce\ is sampled only when a new external address is loaded. 92 ce2\ input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 97 ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. 86 oe\ input output enable: this active low, asynchronous input enables the data i/o output drivers. 83 adv\ input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access after the external address is loaded. a high on this pin effectively causes wait states to be generated (no address advance). to ensure use of correct address during write cycle, adv\ must be high at the rising edge of the first clock after an adsp\ cycle is initiated. 84 adsp\ input synchronous address status processor: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc\, but dependent upon ce\, ce2, and ce2\. adsp\ is ignored if ce\ is high. power-down state is entered if ce2 if low or ce2\ is high. 85 adsc\ input synchronous address status controller: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read or write is performed using the new address if ce\ is low. adsc\ is also used to place the chip into power- down state when ce\ is high. 31 mode input mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. do not alter input state while device is operating. 64 zz input snooze enable: this active high, asynchronous input causes the device to enter a low- power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. (a) 58, 59, 62, 63, 68, 69, 72, 73 (b) 8, 9, 12,13, 18, 19, 22 , 23 dqa dqb input/ output sram data i/os: byte "a" is dqa pins; byte "b" is dqb pins. input data must meet setup and hold times around the rising edge of clk. 74, 24 nc/dqpa nc/dqpb nc/ i/o no connect/parity data i/os: byte "a" is dqpa pins; byte "b" is dqpb pins. 15, 41,65, 91 vdd supply power supply: see dc electrical characteristics and operating conditions for range. 4, 11, 20, 27, 54, 61, 70, 77 vddq supply isolated output buffer supply: see dc electrical characterics and operating conditions for range. 5, 10, 14, 17, 21, 26, 40, 55, 60, 67 71, 76, 90 vss supply ground: gnd 38, 39 dnu --- do not use: these signals may either be unconnected or wired to gnd to improve package heat dissipation. 1-3, 6, 7, 16,25, 28-30, 51-53, 56,57, 66, 75, 78, 79, 95, 96 nc ----- no connect: these signals are not internally connected and may be connected to ground to improve package heat dissipation. 42, 43 nf no function: these pins are internally connected to the die and will have the capacitance of input pins. it is allowable to leave these pins unconnected or driven by signals.
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 ssram as5ss256k18 austin semiconductor, inc. interleaved burst address table (mode=nc or high) linear burst address table (mode=low) functional block diagram note: the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information. 18 18 16 18 sa0, sa1, sa mode adv\ clk adsc\ adsp\ bwb\ bwa\ bwe\ gw\ ce\ ce2 ce2\ oe\ 2 address register binary counter and logic byte "b" write register byte "a" write register enable register clr q1 q0 sa1' sa0' input registers output buffers sense amps 256k x 9 x 2 memory array 9 9 byte "b" write driver byte "a" write driver 9 9 18 18 18 18 dqs dqpa dqpb 2 sa0-sa1 first address (external) second address (internal) third address (internal) fourth address (internal) xx00 xx01 xx10 xx11 xx01 xx00 xx11 xx10 xx10 xx11 xx00 xx01 xx11 xx10 xx01 xx00 first address (external) second address (internal) third address (internal) fourth address (internal) xx00 xx01 xx10 xx11 xx01 xx10 xx11 xx00 xx10 xx11 xx00 xx01 xx11 xx00 xx01 xx10 partial truth table for write commands function gw\ bwe\ bwa\ bwb\ read h h x x read h l h h write byte "a" h l l h write byte "b" h l h l write all bytes h l l l write all bytes l x x x note: using bwe\ and bwa\ through bwb\, any one or more bytes may be written.
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 ssram as5ss256k18 austin semiconductor, inc. truth table notes: 1. x means dont care. \ means active low. h means logic high. l means logic low. 2. for write\, l means any one or more byte write enable signals (bwa\, bwb\) and bwe\ are low or gw\ is low. write\ = h for a ll bwx\, bwe\, gw\ high. 3. bwa\ enables writes to dqas and dqpa. bwb\ enables writes to dqbs and dqpb. 4. all inputs except oe\ and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe\ must be high before the input data setup time and held high throughout the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp\ low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe\ low or gw\ low for the subsequent l-h edge of clk. refer to write timing diagram for clarification. operation address used ce\ ce2\ ce2 zz adsp\ adsc\ adv\ write\ oe\ clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ssram as5ss256k18 austin semiconductor, inc. absolute maximum ratings* voltage on v dd supply relative to v ss ............-0.5v to +4.6v voltage on v dd q supply relative to v ss .........-0.5v to +4.6v storage temperature (plastic) .....................-55 c to +125 c max junction temperature**.......................................+150 c short circuit output current.....................................100ma *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. **maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. dc electrical characteristics and recommended operating conditions (-55 o c < t a < +125 o c and -40 o c -0.7v for t < t kc/2 for i < 20ma power-up: v ih < +3.6v and v dd <3.135v for t < 200ms 3. mode pin has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 2 for 3.3v i/o. ac load current is higher then the stated dc values. 5. v dd q should never exceed v dd . v dd and v dd q can be connected together, for 3.3v i/o operation only. 6. this parameter is sampled. capacitance description conditions sym max units notes control input capacitance c i 4pf6 input/output capacitance (dq) c o 5pf6 address capacitance c a 3.5 pf 6 clock capacitance c ck 3.5 pf 6 t a = 25c; f = 1mhz; v dd = 3.3v thermal resistance description conditions sym typ units notes thermal resistance (junction to ambient) q ja 46 c/w 6 thermal resistance (junction to top of case) q jc 2.8 c/w 6 test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 ssram as5ss256k18 austin semiconductor, inc. i dd electrical characteristics and recommended operating conditions (-55 o c < t a < +125 o c and -40 o c v ih ; cycle time > t kc (min); v dd = max; outputs open i dd 375 325 250 ma 2, 3, 4 power supply current: idle device selected; v dd = max; adsc\, adsp\, adv\, gw\, bwx\ > v ih ; all inputs < v ss +0.2 or > v dd q -0.2; cycle time > t kc (min); outputs open i dd1 100 85 65 ma 2, 3, 4 cmos standby device deselected; v dd = max; all inputs < vss +0.2 or > v dd q -0.2; all inputs static; clk frequency =0 i sb2 10 10 10 ma 3, 4 ttl standby device deselected; v dd = max; all inputs < v il or > v ih ; all inputs static; clk frequency = 0 i sb3 25 25 25 ma 3, 4 clock running device deselected; v dd = max; asdp\, adv\, gw\, bwx\ > v ih ; all inputs < v ss +0.2 or > v dd q -0.2; cycle time > t kc (min) i sb4 100 85 65 ma 3, 4 power supply current: operating parameter max notes: 1. v dd q = +3.3v +0.3v/-0.165v for 3.3v i/o configuration. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. device deselected means device is in power-down mode as defined in the truth table. device selected means device is active (not in power-down mode). 4. typical values are measured at 3.3v, 25c and 15ns cycle time.
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 ssram as5ss256k18 austin semiconductor, inc. electrical characteristics and recommended ac operating conditions (note 1) -55 o c < t a < +125 o c and -40 o c as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 ssram as5ss256k18 austin semiconductor, inc. ac test conditions output loads v ih = (v dd /2.2) + 1.5v v il = (v dd /2.2) - 1.5v input rise and fall times 1ns input timing reference levels v dd /2.2 output reference levels v dd q/2.2 output load see figures 1 and 2 input pulse levels 3.3v dq fig. 2 output load equivalent 351 w 5 pf 317 w fig. 1 output load equivalent dq 50 w z 0 =50 w vt = 1.5v load derating curves asis 256k x 18 synchronous burst sram timing is dependent upon the capacitive loading on the outputs. snooze mode snooze mode is a low-current, power-down mode in which the device is deselected and current is reduced to i sb2z . the duration of snooze mode is dictated by the length of time zz is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, i sb2z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not quaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. * except zz 1 23 4 1 23 4 1 23 4 1234 dont care snooze mode waveform description conditions sym min max units notes current during snooze mode zz > v ih i sb2z 10 ma zz active to input ignored t zz t kc ns 1 zz inactive to input sampled t rzz t kc ns 1 zz active to snooze current t zzi t kc ns 1 zz inactive to exit snooze current t rzzi 0ns1 snooze mode electrical characteristics note: 1. this parameter is sampled. 12345 12345 12345 12345 12345 12345 12345 12345 1234567890 1 23456789 0 1 23456789 0 1234567890 1 1 1 1 12 12 12 12 t zz t rzz t zzi i sb2 t rzzi clk zz i supply all inputs*
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 ssram as5ss256k18 austin semiconductor, inc. read timing note: 1. q(a2) referes to output from address a2. q(a2+1) refers to output from the next internal burst address following a2. 2. ce2\ and ce2 have timing identical to ce\. on this diagram, when ce\ is low, ce2\ is low and ce2 is high. when ce\ is hig h, ce2\ is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. 4. outputs are disabled t kqhz after deselect. read timing parameters min max min max min max min max min max min max t kc 8.8 10 15 ns t as 1.5 1.8 2.0 ns t kf 113 100 66 mhz t adss 1.5 1.8 2.0 ns t kh 2.5 3.0 4.0 ns t aas 1.5 1.8 2.0 ns t kl 2.5 3.0 4.0 ns t ws 1.5 1.8 2.0 ns t kq 7.5 8.5 10 ns t ces 1.5 1.8 2.0 ns t kqx 1.5 3.0 3.0 ns t ah 0.5 0.5 0.5 ns t kqlz 1.5 3.0 3.0 ns t adsh 0.5 0.5 0.5 ns t kqhz 4.2 5.0 5.0 ns t aah 0.5 0.5 0.5 ns t oeq 4.2 5.0 5.0 ns t wh 0.5 0.5 0.5 ns t oelz 000 ns t ceh 0.5 0.5 0.5 ns t oehz 4.2 5.0 5.0 ns -10 -9 -8 sym -10 units units sym -8 -9 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 1234 1234 1234 1234 1234 1234 1234 12345 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 1 1 1 1 1 1 clk adsp\ adsc\ address a2 bwe\, gw\, bwa\-bwb\ ce\ (note 2) adv\ oe\ single read burst read q 12345 12345 12345 12345 12345 12345 a1 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 1 2 3 1 2 3 123 12345678 12345678 12345678 12345678 12345678 12345678 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 1 234567890123456789012345678901212345678901234567890123456789012123456789012345678 9 1 234567890123456789012345678901212345678901234567890123456789012123456789012345678 9 1 234567890123456789012345678901212345678901234567890123456789012123456789012345678 9 1 234567890123456789012345678901212345678901234567890123456789012123456789012345678 9 12345678901234567890123456789012123456789012345678901234567890121234567890123456789 12 12 12 12 12 12 q(a2) q(a2+2) 12 12 12 12 12 12 12 12 12 12 12 12 q(a2+3) 12 12 12 12 12 12 q(a2) 123 123 123 123 123 123 q(a2+1) 12 12 12 12 12 12 q(a2+2) 123456 123456 123456 123456 123456 123456 1234567 1234567 1234567 1234567 1234567 1234567 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678 12345678 12345678 12345678 12345678 12345678 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 12 12 12 12 12 12 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 q(a1) q(a2+1) 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234567 1234567 1234567 1234567 1234567 1234567 1234567 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 12 12 12 12 12 12 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567 123456 123456 123456 123456 123456 123456 123456 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1 23456789012345678901 2 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 12 12 12 12 12 12 123456789012 123456789012 123456789012 123456789012 123456789012 123456789012 123456789012 123456 1 2345 6 1 2345 6 1 2345 6 1 2345 6 1 2345 6 123456 1 1 1 1 1 1 123 123 123 123 1234 1234 1234 1234 1234 1234 1234 1234 t adss t adsh 123456 123456 123456 123456 123456 123456 123456 t as t ah t kc t kl t kh t adss t adsh t ws t wh t ces t ceh 123456 123456 123456 123456 123456 123456 123456 t aas t aah adv\ suspends burst. high-z t oehz t kqlz t kq t oeq t oelz t kq t kqx t kqhz burst wraps around to its initial state. (note 1) deselect cycle (note 4)
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 ssram as5ss256k18 austin semiconductor, inc. note: 1. d(a2) refers to output from address a2. d(a2+1) refres to output from the next internal burst address following a2. 2. ce2\ and ce2 have timing identical to ce\. on this diagram, when ce\ is low, ce2\ is low and ce2 is high. when ce\ is high , ce2\ is high and ce2 is low. 3. oe\ must be high before the input data setup and held high throughout the data hold time. this prevents input/output data c ontention for the time period prior to the byte write enable inputs being sampled. 4. adv\ must be high to permit a write to the loaded address. 5. full-width write can be initiated by gw\ low; or gw\ high and bwe\, bwa\ and bwb\ low. write timing min max min max min max min max min max min max t kc 8.8 10 15 ns t ds 1.5 1.8 2.0 ns t kf 113 100 66 mhz t ces 1.5 1.8 2.0 ns t kh 2.5 3.0 4.0 ns t ah 0.5 0.5 0.5 ns t kl 2.5 3.0 4.0 ns t adsh 0.5 0.5 0.5 ns t oehz 4.2 5.0 5.0 ns t aah 0.5 0.5 0.5 ns t as 1.5 1.8 2.0 ns t wh 0.5 0.5 0.5 ns t adss 1.5 1.8 2.0 ns t dh 0.5 0.5 0.5 ns t aas 1.5 1.8 2.0 ns t ceh 0.5 0.5 0.5 ns t ws 1.5 1.8 2.0 ns -10 -9 -8 sym -10 units units sym -8 -9 write timing parameters 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 1234 1234 1234 1234 1234 1234 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1234567890 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1234567890 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1234 1234 123456789012 123456789012 123456789012 123456789012 123456789012 123456789012 123456789012 123456 1 2345 6 1 2345 6 1 2345 6 1 2345 6 1 2345 6 123456 12 12 12 12 12 12 12 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1234567890 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1234 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234567890 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1 23456789 0 1234567890 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 clk adsp\ adsc\ address a2 bew\, bwa\ - bwb\ ce\ (note 2) adv\ oe\ single write burst write gw\ d extended burst write 1234 1234 1234 1234 1234 1234 a1 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 1 2 3 1 2 3 123 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 12 12 12 12 12 12 1 1 1 1 1 1 a3 12345678 12345678 12345678 12345678 12345678 12345678 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 12 12 12 12 12 12 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 1234567890123456789012345678901212345678901234567890123456789012123456789012 1 23456789012345678901234567890121234567890123456789012345678901212345678901 2 1 23456789012345678901234567890121234567890123456789012345678901212345678901 2 1 23456789012345678901234567890121234567890123456789012345678901212345678901 2 1 23456789012345678901234567890121234567890123456789012345678901212345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012 d(a2) d(a2+2) 12 12 12 12 12 d(a2+3) 12 12 12 12 12 d(a3) 12 12 12 12 12 d(a3+1) 12 12 12 12 12 d(a3+2) 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234 1234 1234 1234 1234 1234 1234 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234567 1234567 1234567 1234567 1234567 1234567 1234567 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678 12345678 12345678 12345678 12345678 12345678 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 12 12 12 12 12 12 1234 1234 1234 1234 1234 1234 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234 1234 1234 1234 1234 1234 1234567890123456789012345678901212345678901234567890 1 23456789012345678901234567890121234567890123456789 0 1 23456789012345678901234567890121234567890123456789 0 1 23456789012345678901234567890121234567890123456789 0 1 23456789012345678901234567890121234567890123456789 0 1 23456789012345678901234567890121234567890123456789 0 1234567890123456789012345678901212345678901234567890 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 12 12 12 12 12 12 12 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 d(a1) d(a2+1) t adss t adsh t kc t kl t kh t as t ah 123456 123456 123456 123456 123456 123456 123456 t adss t adsh 123456 123456 123456 123456 123456 123456 123456 adsc\ extends burst. byte write signals are ignored when adsp\ is low. t ws t wh t ws t wh (note 5) 123456 123456 123456 123456 123456 123456 123456 123456789 123456789 123456789 123456789 123456789 123456789 123456789 123456789 123456789 123456789 123456789 123456789 1234567 1234567 1234567 1234567 1234567 1234567 123456789 123456789 123456789 123456789 123456789 123456789 12345 1 234 5 1 234 5 1 234 5 1 234 5 12345 t ces t ceh t aas t aah (note 4) adv\ suspends burst. (note 3) q 1234 1234 1234 12345 12345 12345 123456 12345 6 123456 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 t oehz 123 123 123 123 12 12 12 12 12 12 d(a2+1) 123 123 123 123 12 12 12 12 12 12 (note 1) high-z burst read 12345 1 234 5 1 234 5 12345 dont care t ds t dh 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345678901234567
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 ssram as5ss256k18 austin semiconductor, inc. note: 1. q(a4) refers to output from address a4. q(a4+1) refers to output from the next internal burst address following a4. 2. ce2\ and ce2 have timing identical to ce\. on this diagram, when ce\ is low, ce2\ is low and ce2 is high. when ce\ is high , ce2\ is high and ce2 is low. 3. the data bus (q) remains in high-z following a write cycle unless an adsp\, adsc\, or adv\ cycle is performed. 4. gw\ is high. 5. back-to-back reads may be controlled by either adsp\ or adsc\. 6. timing is shown assuming that the device was not enabled before entering into this sequence. read/write timing 6 min max min max min max min max min max min max t kc 8.8 10 15 ns t ws 1.5 1.8 2.0 ns t kf 113 100 66 mhz t ds 1.5 1.8 2.0 ns t kh 2.5 3.0 4.0 ns t ces 1.5 1.8 2.0 ns t kl 2.5 3.0 4.0 ns t ah 0.5 0.5 0.5 ns t kq 7.5 8.5 10 ns t adsh 0.5 0.5 0.5 ns t oelz 000 ns t wh 0.5 0.5 0.5 ns t oehz 3.5 4.2 5.0 ns t dh 0.5 0.5 0.5 ns t as 1.5 1.8 2.0 ns t ceh 0.5 0.5 0.5 ns t adss 1.5 1.8 2.0 ns -10 -9 -8 sym -10 units units sym -8 -9 read/write parameters 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 clk adsp\ adsc\ address a2 bwe\, gw\ bwa\ - bwb\ ce\ (note 2) adv\ oe\ back-to-back reads (note 5) burst read d back-to-back write?s 12345 12345 12345 12345 12345 12345 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 1 2 3 1 2 3 123 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678901234567890123456789012123 1 234567890123456789012345678901212 3 1 234567890123456789012345678901212 3 1 234567890123456789012345678901212 3 1 234567890123456789012345678901212 3 12345678901234567890123456789012123 12 12 12 12 12 12 1 1 1 1 1 1 a5 d(a5) d(a6) 123456 123456 123456 123456 123456 123456 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 123456789012345 1234567890123456789012345678901212345678 123456789012345678901234567890121234567 8 123456789012345678901234567890121234567 8 123456789012345678901234567890121234567 8 123456789012345678901234567890121234567 8 123456789012345678901234567890121234567 8 1234567890123456789012345678901212345678 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 12345 12345 12345 12345 12345 12345 12345 d(a3) 12345 12345 12345 12345 12345 12345 a1 a3 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 1 2 3 1 2 3 123 a4 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345678901234567890123456789012123456789012 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 1 234567890123456789012345678901212345678901 2 12345678901234567890123456789012123456789012 12 12 12 12 12 12 single write t kc t kl t kh t adss t adsh 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123 123 123 123 123 123 a6 123 123 123 123 123 123 t as 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 t ah 123456 123456 123456 123456 123456 123456 123456 123456 12345 12345 12345 12345 12345 12345 12345 12345 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123456789 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 1 2345678 9 123456789 1234 1234 1234 1234 1234 1234 1234 12345 12345 12345 12345 12345 12345 123456 123456 123456 123456 123456 123456 123456 123456 t ces t ceh t ws t wh 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345678901234567 12345678901234567 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 123456 1234 1234 1234 1234 q(a1) 123 123 123 123 q(a2) q(a4) q(a4+1) 12 12 12 12 12 12 q(a4+2) 12 12 12 12 12 12 q(a4+3) 1 1 1 1 1 1 12 12 12 12 12 12 q high-z t ds t dh t oelz t kq (note 1) 123456 1 2345 6 1 2345 6 1 2345 6 123456 dont care 12345 1 234 5 1 234 5 1 234 5 12345 undefined t oehz
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 ssram as5ss256k18 austin semiconductor, inc. mechanical definitions asi case #1001 (package designator dq) 16.00 +0.20/-0.05 14.00 + 0.10 22.10 + 0.10/-0.15 20.10 + 0.10 0.62 pin #1 id note: 1. all dimensions in millimeters (max/min) or typical where noted. 2. package width and length do not include mold protrusion; allowable mold protursion is 0.25mm per side. 1.00 typ detail a 0.10 +0.10/-0.05 gage plane 0.25 0.60 + 0.15 0.32 +0.06/-0.10 0.65 1.50 + 0.10 1.40 + 0.05 0.10 see detail a 0.15 +0.03/-0.02
as5ss256k18 rev. 2.0 12/00 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 ssram as5ss256k18 austin semiconductor, inc. example: as5ss256k18dq-8/it device number package type speed ns process as5ss256k18 dq -8 it only as5ss256k18 dq -9 /* as5ss256k18 dq -10 /* ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c

▲Up To Search▲

Price & Availability of AS5SS256K18DQ-10IT

	To Download AS5SS256K18DQ-10IT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .